Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique

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2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	Roel Pantonial, Md. Ashfaquzzaman Khan, Naoto Miyamoto, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi, "Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique," Asia and South Pacific Design Automation Conference, pp. 108-109, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.357964, author = {Roel Pantonial and Md. Ashfaquzzaman Khan and Naoto Miyamoto and Koji Kotani and Shigetoshi Sugawa and Tadahiro Ohmi}, title = {Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {108-109}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357964}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique SN - 1-4244-0629-3 SP108 EP109 A1 - Roel Pantonial, A1 - Md. Ashfaquzzaman Khan, A1 - Naoto Miyamoto, A1 - Koji Kotani, A1 - Shigetoshi Sugawa, A1 - Tadahiro Ohmi, PY - 2007 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Roel Pantonial, Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85

Md. Ashfaquzzaman Khan, Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85

Naoto Miyamoto, New Industry Creation Hatchery Center, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai,

Koji Kotani, Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85

Shigetoshi Sugawa, Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85

Tadahiro Ohmi, New Industry Creation Hatchery Center, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai,

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357964

This paper studies issues concerning dynamically reconfigurable FPGA (DRFPGA). It reports the architecture and performance of Flexible Processor III (FP3), a newly proposed DRFPGA. The FP3 employs a new shift register-type temporal interconnect to reduce operation delay. Designed and fabricated in 0.35um 2P3M CMOS technology, FP3 works correctly as a multi-context FPGA. Our experimental results show that there exist cases where the best user circuit speed was achieved when 2 contexts were in use for a benchmark circuit. This is because of the reduction of buffers in the critical path by temporal partitioning.

Citation:

Roel Pantonial, Md. Ashfaquzzaman Khan, Naoto Miyamoto, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi, "Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique," asp-dac, pp.108-109, 2007 Asia and South Pacific Design Automation Conference, 2007

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