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2007 Asia and South Pacific Design Automation Conference
A 2.8-V Multibit Complex Bandpass ??AD Modulator in 0.18?m CMOS
Yokohama
January 23-January 26
ISBN: 1-4244-0629-3
ASCII Text
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H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, H. Kobayashi, M. Hotta, "A 2.8-V Multibit Complex Bandpass ??AD Modulator in 0.18?m CMOS," Asia and South Pacific Design Automation Conference, pp. 96-97, 2007 Asia and South Pacific Design Automation Conference, 2007.
 
 
BibTex
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@article{ 10.1109/ASPDAC.2007.357958,
author = {H. San and Y. Jingu and H. Wada and H. Hagiwara and A. Hayakawa and H. Kobayashi and M. Hotta},
title = {A 2.8-V Multibit Complex Bandpass ??AD Modulator in 0.18?m CMOS},
journal ={Asia and South Pacific Design Automation Conference},
volume = {0},
year = {2007},
isbn = {1-4244-0629-3},
pages = {96-97},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357958},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asia and South Pacific Design Automation Conference
TI - A 2.8-V Multibit Complex Bandpass ??AD Modulator in 0.18?m CMOS
SN - 1-4244-0629-3
SP96
EP97
A1 - H. San,
A1 - Y. Jingu,
A1 - H. Wada,
A1 - H. Hagiwara,
A1 - A. Hayakawa,
A1 - H. Kobayashi,
A1 - M. Hotta,
PY - 2007
KW - 2.8 V
KW - bandpass delta-sigma AD modulator
KW - second-order AD modulator
KW - multibit switched-capacitor AD modulator
KW - low-IF receivers
KW - wireless communication systems
KW - signal-to-noise-and-distortion
KW - complex bandpass filter
KW - dynamic matching
KW - data-weighted averaging algorithm
KW - CMOS process
KW - 78 kHz
KW - 28.4 mW
KW - 0.18 micron
VL - 0
JA - Asia and South Pacific Design Automation Conference
ER -
 
H. San, Dept. of Electron. Eng., Gunma Univ.
Y. Jingu, Dept. of Electron. Eng., Gunma Univ.
H. Wada, Dept. of Electron. Eng., Gunma Univ.
H. Hagiwara, Dept. of Electron. Eng., Gunma Univ.
A. Hayakawa, Dept. of Electron. Eng., Gunma Univ.
H. Kobayashi, Dept. of Electron. Eng., Gunma Univ.
A second-order multibit switched-capacitor (SC) complex bandpass DeltaSigma AD modulator has been designed, fabricated and tested for application to low-IF receivers in wireless communication systems. We have employed two new algorithms there to improve the signal-to-noise-and-distortion (SNDR) of the modulator, (i) A complex bandpass filter with I, Q dynamic matching to reduce the mismatch influence between I, Q paths. As its by-product, the complex modulator can be divided into two separate parts without signal line crossing between the upper and lower paths. Therefore, the layout design of the modulator can be greatly simplified; (ii) A new complex bandpass data-weighted averaging (DWA) algorithm is implemented to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy. Implemented in a 0.18-mum CMOS process and at 2.8V supply, the modulator achieves a measured peak SNDR of 64.5dB at 20MS/s with a signal bandwidth of 78kHz while dissipating 28.4mW and occupying an area of 1.82mm2.
Index Terms:
2.8 V, bandpass delta-sigma AD modulator, second-order AD modulator, multibit switched-capacitor AD modulator, low-IF receivers, wireless communication systems, signal-to-noise-and-distortion, complex bandpass filter, dynamic matching, data-weighted averaging algorithm, CMOS process, 78 kHz, 28.4 mW, 0.18 micron
Citation:
H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, H. Kobayashi, M. Hotta, "A 2.8-V Multibit Complex Bandpass ??AD Modulator in 0.18?m CMOS," asp-dac, pp.96-97, 2007 Asia and South Pacific Design Automation Conference, 2007
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