A Programmable Fully-Integrated GPS receiver in 0.18?m CMOS with Test Circuits

A
ASP-DAC
2007
2007 Asia and South Pacific Design Automation Conference
Abstract - A Programmable Fully-Integrated GPS receiver in 0.18?m CMOS with Test Circuits

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2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	Mahta Jenabi, Noushin Riahi, Ali Fotowat-Ahmady, "A Programmable Fully-Integrated GPS receiver in 0.18?m CMOS with Test Circuits," Asia and South Pacific Design Automation Conference, pp. 80-85, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.357796, author = {Mahta Jenabi and Noushin Riahi and Ali Fotowat-Ahmady}, title = {A Programmable Fully-Integrated GPS receiver in 0.18?m CMOS with Test Circuits}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {80-85}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357796}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - A Programmable Fully-Integrated GPS receiver in 0.18?m CMOS with Test Circuits SN - 1-4244-0629-3 SP80 EP85 A1 - Mahta Jenabi, A1 - Noushin Riahi, A1 - Ali Fotowat-Ahmady, PY - 2007 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Mahta Jenabi, RF IC designer, Unistar Micro Technology Inc, Richmond Hill, ON L4C 0K1. Tel: +1-905-780-1347, Fax:

Noushin Riahi, RF IC designer, Unistar Micro Technology Inc, Richmond Hill, ON L4C 0K1. Tel: +1-905-780-1347, Fax:

Ali Fotowat-Ahmady, RF IC designer, Unistar Micro Technology Inc, Richmond Hill, ON L4C 0K1. Tel: +1-905-780-1347, Fax:

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357796

A 0.18?m single chip GPS receiver with 19.5 mA power consumption is implemented in 6.5 mm2. A serial input digital control with additional testing structure not adding more than 4% to the Si area are used to the actual RF circuits in case of problems minimizing the number of Si runs.

Citation:

Mahta Jenabi, Noushin Riahi, Ali Fotowat-Ahmady, "A Programmable Fully-Integrated GPS receiver in 0.18?m CMOS with Test Circuits," asp-dac, pp.80-85, 2007 Asia and South Pacific Design Automation Conference, 2007

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