Directed tes program-based verification or formal verification methods are usually quite ineffective on large cache-coherent, non-uniform memory access (CC-NUMA) multi-processors because of the size and complexity of the design and the complexity of the cache-coherence protocol. A controllable biased/constrained random stimuli generator coupled with an error detection mechanism using scoreboards and feedback with coverage analysis tools is a promising alternative methodology. We applied this methodology to verify a shared memory and message passing multiprocessor system consisting of 32 and 64 bit processor-based symmetric multiprocessing (SMP) servers connected by a proprietary cache coherent router-based interconnect fabric. This paper describes the problems faced, solutions implemented, and design decisions taken to design the scoreboard and discusses the errors found by this methodology.