A Power Minimization Technique for Arithmetic Circuits by Cell Selection

V
VLSID
2002
ASP-DAC/VLSI Design 2002
Abstract - A Power Minimization Technique for Arithmetic Circuits by Cell Selection

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ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	Masanori Muroyama, Akihiko Hyodo, Hiroto Yasuura, Tohru Ishihara, "A Power Minimization Technique for Arithmetic Circuits by Cell Selection," VLSI Design, International Conference on, pp. 268, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.994933, author = {Masanori Muroyama and Akihiko Hyodo and Hiroto Yasuura and Tohru Ishihara}, title = {A Power Minimization Technique for Arithmetic Circuits by Cell Selection}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {268}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994933}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A Power Minimization Technique for Arithmetic Circuits by Cell Selection SN - 0-7695-1441-3 SP EP A1 - Masanori Muroyama, A1 - Akihiko Hyodo, A1 - Hiroto Yasuura, A1 - Tohru Ishihara, PY - 2002 KW - low power KW - cell based design KW - arithmetic circuits VL - 0 JA - VLSI Design, International Conference on ER -

Masanori Muroyama, Kyushu University

Akihiko Hyodo, Kyushu University

Hiroto Yasuura, Kyushu University

Tohru Ishihara, University of Tokyo

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994933

1bit full adders and counters are usually used as basic cells in the arithmetic circuits. Characteristics of these components have strong impact on power, delay, and area of the arithmetic circuits. In this paper we propose a design method for low power arithmetic circuits, which the designer selects basic cells from a set of circuits with different structures(symmetrical one and asymmetrical one) by the method and the mothod optimizes connections to the terminals of the basic cells. Experimental results demonstrate 32.1% power reduction of a parallel multiplier designed by the proposed technique.

Index Terms:

low power, cell based design, arithmetic circuits

Citation:

Masanori Muroyama, Akihiko Hyodo, Hiroto Yasuura, Tohru Ishihara, "A Power Minimization Technique for Arithmetic Circuits by Cell Selection," vlsid, pp.268, ASP-DAC/VLSI Design 2002, 2002

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