Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99) Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits Wanchai, Hong Kong January 18-January 21 ISBN: 0-7803-5012-X
A symbolic fault simulator is integrated in a Genetic Algorithm (GA) environment to perform Automatic Test Pattern Generation (ATPG) for synchronous sequential circuits. In a two phase algorithm test length and fault coverage as well are optimized. However, there are circuits with bad random testability properties, that are also hard to test using genetically optimized test patterns. Thus, deterministic aspects are included in the GA environment to improve fault coverage. Experiments demonstrate that tests with higher fault coverages and considerably shorter test sequences than in previously presented approaches are obtained.
Citation:
Martin Keim, Nicole Drechsler, Bernd Becker, "Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits," asp-dac, pp.315, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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