An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection

A
ASP-DAC
1999
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)
Abstract - An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection

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	Similar Articles Articles by Shin'ichi Wakabayashi Articles by Tetsushi Koide Articles by Naoyoshi Toshine Articles by Mutsuaki Goto Articles by Yoshikatsu Nakayama Articles by Koichi Hatta

Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)

Wanchai, Hong Kong

January 18-January 21

ISBN: 0-7803-5012-X

	ASCII Text	x
	Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta, "An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection," Asia and South Pacific Design Automation Conference, pp. 37, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999.

	BibTex	x
	@article{ 10.1109/ASPDAC.1999.759704, author = {Shin'ichi Wakabayashi and Tetsushi Koide and Naoyoshi Toshine and Mutsuaki Goto and Yoshikatsu Nakayama and Koichi Hatta}, title = {An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {1999}, isbn = {0-7803-5012-X}, pages = {37}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759704}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection SN - 0-7803-5012-X SP EP A1 - Shin'ichi Wakabayashi, A1 - Tetsushi Koide, A1 - Naoyoshi Toshine, A1 - Mutsuaki Goto, A1 - Yoshikatsu Nakayama, A1 - Koichi Hatta, PY - 1999 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Shin'ichi Wakabayashi, Hiroshima University, Japan

Tetsushi Koide, Hiroshima University, Japan

Naoyoshi Toshine, Hiroshima University, Japan

Mutsuaki Goto, Hiroshima University, Japan

Yoshikatsu Nakayama, Hiroshima University, Japan

Koichi Hatta, Hiroshima University, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759704

This paper describes an LSI implementation of a genetic algorithm (GA), called the Genetic Algorithm Accelerator (GAA) chip. The GAA chip is an LSI implementation of a GA, in which two types of crossover operators are supported, and the operator to be actually used in the algorithm is not fixed in advance, but dynamically selected for each pair of chromosomes in the algorithm execution. The GAA chip has been designed with the Verilog HDL and simulated with some benchmark functions. According to the simulation, the GAA chip will run with 50MHz clock in maximum. The chip has been fabricated with the CMOS 0.5 μm standard cell technology.

Citation:

Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta, "An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection," asp-dac, pp.37, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999

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