This paper introduces the concepts underlying a new digital computational fabric called an Elemental Computing Array (ECA). This computation fabric is designed to implement logic resiliency at the very lowest level of design. Current design practices assume the inherent unreliability of silicon dedicated to memory functions, the inherent unreliability of interconnects at the box, board and IC level yet paradoxically still assumes full reliability of silicon dedicated to logic functions. The combination of software constructs and hardware architectural constructs in the ECA architecture allows system designs to become inherently resilient to fabrication defects, run-time transient faults and device wear out faults.