IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06) Pipelined Range Reduction for Floating Point Numbers Steamboat Springs, Colorado, USA September 11-September 13 ISBN: 0-7695-2682-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.53
This paper presents a new pipelined architecture to deal with range reduction for floating point representation. It is based on Horner?s scheme and a look-up table. The overall design has been optimized for a module equal to 2?, which is the most widely used due to trigonometric functions requirements. To ensure an accuracy of one unit in the last place (ULP), a complete error propagation study has been carried out.
Citation:
Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata, "Pipelined Range Reduction for Floating Point Numbers," asap, pp.145-152, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||