IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06) Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder Steamboat Springs, Colorado, USA September 11-September 13 ISBN: 0-7695-2682-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.50
This paper describes the implementation of a 256-state, rate 14, soft-decision Viterbi decodel: The implementation explores several variables and design considerations of a Viterbi decodel; testing various methods for low power and throughput capability. By designing the Viterbi decoder using three techniques, a progressive active ACS (Add- Compare-Select), prediction matchel; and reduced read traceback, we take the most efJicient techniques and apply them iteratively to the overall design to achieve 12.7 % of dynamic power consumption with 250Mbps of throughput.
Citation:
Woo Hyung Lee, Pinaki Mazumber, "Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder," asap, pp.182-185, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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