IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06) A Cost Effective Pipelined Divider for Double Precision Floating Point Number Steamboat Springs, Colorado, USA September 11-September 13 ISBN: 0-7695-2682-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.3
The growth of high-performance application in computer graphics, signal processing and scientific computing is a key driver for high performance, fixed latency, pipelined floating point dividers. Solutions available in the literature use large lookup table for double precision floating point operations. In this paper, we propose a cost effective, fixed latency pipelined divider using modified Taylor-series expansion for double precision floating point operations. We reduce chip area by using a smaller lookup table. We show that the latency of the proposed divider is 49.4 times the latency of a full-adder. The proposed divider reduces chip area by about 81% than the pipelined divider in [9] which is based on modified Taylor-series.
Citation:
Sandeep B. Singh, Jayanta Biswas, S. K. Nandy, "A Cost Effective Pipelined Divider for Double Precision Floating Point Number," asap, pp.132-137, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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