Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation

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IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)

Steamboat Springs, Colorado, USA

September 11-September 13

ISBN: 0-7695-2682-9

	ASCII Text	x
	Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro, "Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 360-367, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006.

	BibTex	x
	@article{ 10.1109/ASAP.2006.23, author = {Marjan Karkooti and Predrag Radosavljevic and Joseph R. Cavallaro}, title = {Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {2006}, issn = {1063-6862}, pages = {360-367}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.23}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation SN - 1063-6862 SP360 EP367 A1 - Marjan Karkooti, A1 - Predrag Radosavljevic, A1 - Joseph R. Cavallaro, PY - 2006 KW - null VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

Marjan Karkooti, Rice University, Houston, TX

Predrag Radosavljevic, Rice University, Houston, TX

Joseph R. Cavallaro, Rice University, Houston, TX

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.23

Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper presents a novel flexible decoder architecture for irregular LDPC codes that supports twelve combinations of code lengths -648, 1296, 1944 bits- and code rates- 1/2, 2/3, 3/4, 5/6- based on the IEEE 802.11n standard. All the codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. A prototype of the LDPC decoder has been implemented and tested on a Xilinx FPGA and has been synthesized for ASIC.

Citation:

Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro, "Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation," asap, pp.360-367, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006

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