Architecture design of an H.264/AVC decoder for real-time FPGA implementation

A
ASAP
2006
IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
Abstract - Architecture design of an H.264/AVC decoder for real-time FPGA implementation

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IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)

Steamboat Springs, Colorado, USA

September 11-September 13

ISBN: 0-7695-2682-9

	ASCII Text	x
	Thomas Warsaw, Marcin Lukowiak, "Architecture design of an H.264/AVC decoder for real-time FPGA implementation," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 253-256, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006.

	BibTex	x
	@article{ 10.1109/ASAP.2006.17, author = {Thomas Warsaw and Marcin Lukowiak}, title = {Architecture design of an H.264/AVC decoder for real-time FPGA implementation}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {2006}, issn = {1063-6862}, pages = {253-256}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.17}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - Architecture design of an H.264/AVC decoder for real-time FPGA implementation SN - 1063-6862 SP253 EP256 A1 - Thomas Warsaw, A1 - Marcin Lukowiak, PY - 2006 KW - null VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

Thomas Warsaw, Harris Corporation 1680 University Avenue Rochester, New York

Marcin Lukowiak, Rochester Institute of Technology, Rochester, New York

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.17

This paper discusses hardware development of a realtime H.264/AVC video decoder. Synthesis results are presented for example implementations of the inverse quantization, inverse transform, and deblocking filter stages. A hardware architecture is also proposed for FPGA implementations of a complete video decoder.

Citation:

Thomas Warsaw, Marcin Lukowiak, "Architecture design of an H.264/AVC decoder for real-time FPGA implementation," asap, pp.253-256, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006

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