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IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
An Energy-Delay Efficient Subword Permutation Unit
Steamboat Springs, Colorado, USA
September 11-September 13
ISBN: 0-7695-2682-9
ASCII Text
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Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos, "An Energy-Delay Efficient Subword Permutation Unit," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 245-252, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006.
 
 
BibTex
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@article{ 10.1109/ASAP.2006.10,
author = {Giorgos Dimitrakopoulos and Christos Mavrokefalidis and Costas Galanopoulos and Dimitris Nikolos},
title = {An Energy-Delay Efficient Subword Permutation Unit},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {2006},
issn = {1063-6862},
pages = {245-252},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.10},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - An Energy-Delay Efficient Subword Permutation Unit
SN - 1063-6862
SP245
EP252
A1 - Giorgos Dimitrakopoulos,
A1 - Christos Mavrokefalidis,
A1 - Costas Galanopoulos,
A1 - Dimitris Nikolos,
PY - 2006
KW - null
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
Giorgos Dimitrakopoulos, University of Patras, 26500 Patras, Greece
Christos Mavrokefalidis, University of Patras, 26500 Patras, Greece
Costas Galanopoulos, University of Patras, 26500 Patras, Greece
Dimitris Nikolos, University of Patras, 26500 Patras, Greece
Subword permutations are useful in many multimedia and cryptographic applications. Specialized instructions have been added to the instruction set of general-purpose processors to efficiently implement the required data rearrangements. In this paper, the design of a new energy-delay efficient subword permutation unit is examined. The proposed architecture has been derived by mapping the functionality of one of the most powerful permutation instructions (GRP) to a new enhanced linear sorting network. The introduced subword permutation unit is fast and achieves significant area and energy reductions compared to previous implementations. Also its regularity and its reduced wiring enables efficient VLSI implementations. The efficiency of the proposed architecture has been validated using static CMOS implementations in a standard performance 130nm CMOS technology.
Citation:
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos, "An Energy-Delay Efficient Subword Permutation Unit," asap, pp.245-252, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006
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