2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs Samos, Greece July 23-July 25 ISBN: 0-7695-2407-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2005.68
A Virtual Hierarchical design optimization method has been developed to combine strength of the flat and the hierarchical optimization methods for efficient and quality optimization of multi-million gate designs in a distributed computing environment. A novel design representation "Virtual Hierarchy" is proposed for sub-design optimization in a distributed computing environment. The principle and the implementation details of the method are described. The method has been successfully applied to a number of designs.
Citation:
Thi Nguyen, Kaijian Shi, "Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs," asap, pp.204-212, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||