2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x Samos, Greece July 23-July 25 ISBN: 0-7695-2407-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2005.59
This paper presents small FPGA implementations of low-precision polynomial approximations of functions without multipliers. Our method uses degree-2 or degree-3 polynomial approximations with at most 3-bit coef?cients and low-precision estimations of the powers of x. Here we denote by 3-bit coefficients values with at most 3 non-zero and possibly non-contiguous signed bits (e.g., 1.0010001). This leads to very small operators by replacing the costly multipliers by a small number of additions. Our method provides approximations with very low average error and is suitable for signal processing applications.
Citation:
Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon, "Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x," asap, pp.334-342, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb