2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Instruction Set Architecture Enhancements for Video Processing Samos, Greece July 23-July 25 ISBN: 0-7695-2407-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2005.40
This paper presents some of the enhancements to the TriMedia instruction set architecture (ISA), as supported by the TM3270 media-processor. We show how the new operations are used to optimize the individual MPEG2 encoder kernels. Furthermore, we quantify the contribution of these kernels to overall MPEG2 encoder performance. We introduce two-slot operations, collapsed load operations wit interpolations, and new multiplication operations. The encoder?s texture pipeline for a bi-directionally predicted 8x8 block is performed in 358 VLIW instructions. MPEG2 encoding at CIF resolution at 25 frames per second is achieved within 33.5 MHz. of processor performance.
Citation:
Jan-Willem van de Waerdt, Stamatis Vassiliadis, "Instruction Set Architecture Enhancements for Video Processing," asap, pp.146-153, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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