With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth in commercial, financial, and Internet-based applications, decimal floating point arithmetic is now attracting more attention and hardware support for decimal operations is being considered by various computer manufacturers. In order to standardize decimal number formats and operations, specifications for decimal foatingpoint arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE- 754R). This paper presents an effcient arithmetic algorithm and hardware design for decimal floating-point square root. This design uses an optimized piecewise linear approximation, a modified Newton-Raphson iteration, a specialized rounding technique, and a modifed decimal multiplier. Synthesis results show that a 64-bit (16-digit) implementation of decimal square root, which is compliantwith IEEE-754R, has an estimated critical path delay of 0.95 ns and a maximum latency of 210 clock cycles when implemented using a sequential multiplier and LSI Logic?s 0.11 micron Gfx-P standard cell library.