loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)
Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding
Samos, Greece
July 23-July 25
ISBN: 0-7695-2407-9
Nikolaos Kavvadias, Section of Electronics and Computers, Department of Physics Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece
Spiridon Nikolaidis, Section of Electronics and Computers, Department of Physics Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece

A recent approach to platform-based design involves the use of extensible processors, offering architecture customization possibilities. Part of the designer responsibilities is the domain-specific extension of the baseline processor to fit customer requirements. Key issues of this process are the automated application analysis and candidate instruction identification/selection for implementation as application speci fic functional units (AFUs). In this paper, a design approach that encapsulates automated workload characterization and instruction generation is utilized for extending processors to efficiently support embedded application sets. The method used for instruction generation is a highly parameterized adaptation of the MaxMISO technique, which allows for fast design space exploration. It is proven that only a small number of AFUs are needed in order to support the algorithms of interest (MPEG-4 encoding kernels) and that it is possible to achieve 2? to 3.5? performance improvements although further possibilities such as subword parallelization are not currently regarded.

Citation:
Nikolaos Kavvadias, Spiridon Nikolaidis, "Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding," asap, pp.140-145, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), 2005
Usage of this product signifies your acceptance of the Terms of Use.