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15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'04)
Parallel Montgomery Multipliers
Galveston, Texas
September 27-September 29
ISBN: 0-7695-2226-2
ASCII Text
x 
 
Moboluwaji O. Sanu, Earl E. Swartzlander, Jr., Craig M. Chase, "Parallel Montgomery Multipliers," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 63-72, 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'04), 2004.
 
 
BibTex
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@article{ 10.1109/ASAP.2004.10008,
author = {Moboluwaji O. Sanu and Earl E. Swartzlander, Jr. and Craig M. Chase},
title = {Parallel Montgomery Multipliers},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {2004},
issn = {1063-6862},
pages = {63-72},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2004.10008},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - Parallel Montgomery Multipliers
SN - 1063-6862
SP63
EP72
A1 - Moboluwaji O. Sanu,
A1 - Earl E. Swartzlander, Jr.,
A1 - Craig M. Chase,
PY - 2004
KW - null
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
Moboluwaji O. Sanu, The University of Texas at Austin
Earl E. Swartzlander, Jr., The University of Texas at Austin
Craig M. Chase, The University of Texas at Austin
Modular multiplication is an essential operation in virtually all public-key cryptosystems in use today. This paper presents four designs for speeding up modular multiplication on application-specific crypto-processors. All the approaches utilize small look-up tables and fast, massively parallel multipliers. Two of the approaches trade off smaller look-up tables for a larger, slightly slower multiplier. The other two approaches use larger look-up tables but a smaller, faster multiplier.
Citation:
Moboluwaji O. Sanu, Earl E. Swartzlander, Jr., Craig M. Chase, "Parallel Montgomery Multipliers," asap, pp.63-72, 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'04), 2004
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