The IDEA block cipher is a symmetric-key algorithm which encrypts 64-bit plain text blocks to 64bit ciphertest blocks, using a 128-bit secret key. The security of IDEA relies on combining operations from three groups: integer addition modulo 2⁶, bitwise exclusive or of two 16-bit words, and modified integer multiplication modulo (2⁶ + 1) which is the critical arithmetic operation of the block cipher. This paper is devoted to the study of efficient implementations of this operator on Virtex-II and Virtex-E devices. We investigate three algorithms based on a multiplication with a subsequent modulo correction which are particularly well suited for FPGA device embedding small multiplier blocks. An IDEA processor based on such operators achieves a throughput of 8.5 Gb/s on a Xilinx XC2V1000-6 device. We also describe a new FPGA implementation of a modulo (2⁶ + 1) multiplier proposed by R. Zimmermann. The area of this operator is roughly twice smaller than that of previous FPGA implementations.