A floating-point CORDIC based SVD processor

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	Similar Articles Articles by Z. Liu Articles by K. Dickson Articles by J. V. McCanny

14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03)

The Hague, The Netherlands

June 24-June 26

ISBN: 0-7695-1992-X

	ASCII Text	x
	Z. Liu, K. Dickson, J. V. McCanny, "A floating-point CORDIC based SVD processor," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 194, 14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03), 2003.

	BibTex	x
	@article{ 10.1109/ASAP.2003.1212843, author = {Z. Liu and K. Dickson and J. V. McCanny}, title = {A floating-point CORDIC based SVD processor}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {2003}, issn = {1063-6862}, pages = {194}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212843}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - A floating-point CORDIC based SVD processor SN - 1063-6862 SP EP A1 - Z. Liu, A1 - K. Dickson, A1 - J. V. McCanny, PY - 2003 KW - null VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

Z. Liu, DSiP Laboratories, Queen?s University of Belfast, Belfast, N. Ireland

K. Dickson, DSiP Laboratories, Queen?s University of Belfast, Belfast, N. Ireland

J. V. McCanny, DSiP Laboratories, Queen?s University of Belfast, Belfast, N. Ireland

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212843

An SVD processor system is presented in which each processing element is implemented using a simple CORDIC unit. The internal recursive loop within the CORDIC module is exploited, with pipelining being used to multiplex the two independent micro-rotations onto a single CORDIC processor. This leads to a high performance and efficient hardware architecture. In addition, a novel method for scale factor correction is presented which only need be applied once at the end of the computation. This also reduces the computation time. The net result is an SVD architecture based on a conventional CORDIC approach, which combines high performance with high silicon area efficiency.

Citation:

Z. Liu, K. Dickson, J. V. McCanny, "A floating-point CORDIC based SVD processor," asap, pp.194, 14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03), 2003

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