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13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'02)
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25?m BulkCMOS
San Jose, California
July 17-July 19
ISBN: 0-7695-1712-9
Steven M. Currie, Mayo Foundation
Paul R. Schumacher, Xilinx Inc.
Barry K. Gilbert, Mayo Foundation
Earl E. Swartzlander, University of Texas at Austin
Barbara A. Randall, Mayo Foundation
The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 ?m bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients.Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules; user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module); 5-volt tolerant 3.3-volt I/O; and a command driven interface.
Citation:
Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander, Barbara A. Randall, "Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25?m BulkCMOS," asap, pp.335, 13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'02), 2002
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