13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'02) Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter San Jose, California July 17-July 19 ISBN: 0-7695-1712-9
This paper proposed a method to integrate the AES encrypter and the AES decrypter into a full functional AES crypto-engine. This method can make it a very low-complexity architecture, especially in saving the hardware resource in implementing the AES (Inv)SubBytes module and (Inv)Mixcolumns module, etc. Most designed modules can be used for both AES encryption and decryption. Besides, the architecture can still deliver a high data rate in both en/decryption operations. The proposed architecture is suited for hardware-critical applications, such as smart card, PDA, and mobile phone, etc.
Citation:
Chih-Chung Lu, Shau-Yin Tseng, "Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter," asap, pp.277, 13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'02), 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb