loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'02)
Predictable Instruction Caching for Media Processors
San Jose, California
July 17-July 19
ISBN: 0-7695-1712-9
J. Irwin, University of Bristol
M. D. May, University of Bristol
H. L. Muller, University of Bristol
D. Page, University of Bristol
The determinism of instruction cache performance can be considered a major problem in multimedia devices which hope to maximise their quality of service. If instructions are evicted from the cache by competing blocks of code, the running application will take significantly longer to execute than if the instructions were present. Since it is difficult to predict when this interference will occur, the performance of the algorithm at a given point in time is unclear. We propose the use of an automatically configured partitioned cache to protect regions of the application code from each other and hence minimise interference. As well as being specialised to the purpose of providing predictable performance, this cache can be specialised to the application being run, rather than for the average case, using simple compiler algorithms.
Citation:
J. Irwin, M. D. May, H. L. Muller, D. Page, "Predictable Instruction Caching for Media Processors," asap, pp.141, 13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'02), 2002
Usage of this product signifies your acceptance of the Terms of Use.