A high-radix digit-recurrence algorithm for the computation of the logarithm is presented in this paper. Selection by rounding is used in iterations j ≥ 2, and selection by table in the first iteration is combined with a restricted digit-set for the second one, in order to guarantee the convergence of the algorithm. A sequential architecture is proposed, and the execution time and hardware requirements of this architecture are estimated, for a target precision of n = 32 bits and a radix r = 256. These estimates are obtained according to a rough model for the delay and area cost of the main logic blocks employed, and show the achievement of a speed-up over 4 regarding a conventional radix-2 implementation with redundant arithmetic.