In this paper, we present an approach to determine scheduling functions suitable for the design of processor arrays. The considered scheduling function support a followed LSGP-partitioning of the processor array by allowing executing the tasks of processors of the full-size array mapped into one processor of the partitioned processor array in an arbitrary order. Several constraints are derived to ensure the causality of computations and to prevent access conflicts to both modules and registers.We propose an optimization problem generating the scheduling functions and outline its implementation as an integer linear program. The proposed methods are also applicable for the mapping of algorithms to parallel architectures. In this case, the scheduling function produces identical, independent small threads, which can be combined to utilize the target architecture as much as possible.