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12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00)
A 16-Bit x 16-Bit MAC Design Using Fast 5:2 Compressors
Boston, Massachusetts
July 10-July 12
ISBN: 0-7695-0716-6
ASCII Text
x 
 
Ohsang Kwon, Earl E. Swartzlander, Kevin Nowka, "A 16-Bit x 16-Bit MAC Design Using Fast 5:2 Compressors," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 235, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000.
 
 
BibTex
x
 
@article{ 10.1109/ASAP.2000.862394,
author = {Ohsang Kwon and Earl E. Swartzlander and Kevin Nowka},
title = {A 16-Bit x 16-Bit MAC Design Using Fast 5:2 Compressors},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {2000},
issn = {1063-6862},
pages = {235},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2000.862394},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - A 16-Bit x 16-Bit MAC Design Using Fast 5:2 Compressors
SN - 1063-6862
SP
EP
A1 - Ohsang Kwon,
A1 - Earl E. Swartzlander,
A1 - Kevin Nowka,
PY - 2000
KW - 3:2 counter
KW - 4:2 compressor
KW - 5:2 compressor
KW - multiplier
KW - MAC
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
Ohsang Kwon, University of Texas at Austin
Earl E. Swartzlander, University of Texas at Austin
Kevin Nowka, IBM Austin Research Lab
3:2 counters and/or 4:2 compressors have been widely used for multiplier implementations. In this paper, a new logical decomposition is derived for fast 5:2 compressor and is proposed to be used for 16-bit x 16-bit MAC designs. In addition, when the accumulator output is in carry-save form, one row in partial product matrix can be eliminated before the partial product reduction process. These new methods are combined and explained with 16-bit x 16-bit 2's complement MAC (multiply and accumulate) designs. The use of the new 5:2 compressor leads to 14% speed improvement in the MAC design over the conventional designs using 4:2 compressors and 3:2 counters.
Index Terms:
3:2 counter, 4:2 compressor, 5:2 compressor, multiplier, MAC
Citation:
Ohsang Kwon, Earl E. Swartzlander, Kevin Nowka, "A 16-Bit x 16-Bit MAC Design Using Fast 5:2 Compressors," asap, pp.235, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000
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