12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00)
High Level Synthesis for Peak Power Minimization Using ILP
Boston, Massachusetts
July 10-July 12
ISBN: 0-7695-0716-6
The work presented in this paper focuses on behavioral level power optimization. Specifically, we address the problem of scheduling a data-flow graph under latency constraints. We have developed an integer linear program (ILP) model and a modified force-directed scheduling (MFDS) that minimize the peak power while satisfying timing constraints. Our integer linear programming method extends the traditional ILP approach that minimizes resources to include peak power consideration while adding extensions for multi-cycle and pipelined arithmetic components. In our benchmark results, the peak power is reduced after scheduling based on ILP method and MFDS algorithm and is reduced significantly after scheduling and pipelining are both applied. The results obtained by the heuristic-based algorithms (MFDS) match very well with those obtained by the integer linear programming (ILP) methods. While the results obtained by heuristic-based algorithm are approximate, the results obtained by the integer linear programming methods are optimal. However, the heuristic-based algorithm is faster than the integer linear programming methods.
Index Terms:
Peak power minimization, High-level synthesis, low power design, latency-constrained scheduling, integer linear programming, force-directed scheduling
Citation:
Wen-Tsong Shiue, "High Level Synthesis for Peak Power Minimization Using ILP," asap, pp.103, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000