12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00)
High Level Modeling for Parallel Executions of Nested Loop Algorithms
Boston, Massachusetts
July 10-July 12
ISBN: 0-7695-0716-6
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications (algorithms) and the implementations (architecture), a mapping of the former into the latter, and a simulator for fast execution of the whole. Signal processing algorithms are very often nested-loop algorithms with a high degree of inherent parallelism. This paper presents - for such applications - suitable application and implementation models, a method to convert a given imperative executable specification to a specification in terms of the application model, a method to map this specification into an architecture specification in terms of the implementation model, and a method to analyze the performance through simulation. The methods and tools are illustrated by means of an example.
Citation:
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis, "High Level Modeling for Parallel Executions of Nested Loop Algorithms," asap, pp.79, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000