12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00)
Formal Verification for Microprocessors with Extendable Instruction Set
Boston, Massachusetts
July 10-July 12
ISBN: 0-7695-0716-6
The correctness of processors is a key for their application. Although some verification methods were developed and successfully applied to conventional microprocessors, only a few of them were used in context of application specific devices. This work introduces a formal verification approach for a reconfigurable microprocessor with extendable instruction set. The application of this approach is demonstrated using register transfer description of the CoMPARE processor and the Stanford Validity Checker as prover. Some undesired the verification process found side effects of different instructions that were not discovered during the simulation. In addition, some deficiencies of the hardware description notation as specification formalism were shown.
Index Terms:
reconfigurable processor architecture, pipeline processor, formal verification, abstraction techniques
Citation:
Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube, "Formal Verification for Microprocessors with Extendable Instruction Set," asap, pp.47, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000