A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications

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	Similar Articles Articles by M. Dal Poz Articles by J. Aedo Cobo Articles by W. Van Noije Articles by M. Zuffo

12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00)

Boston, Massachusetts

July 10-July 12

ISBN: 0-7695-0716-6

	ASCII Text	x
	M. Dal Poz, J. Aedo Cobo, W. Van Noije, M. Zuffo, "A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 35, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000.

	BibTex	x
	@article{ 10.1109/ASAP.2000.862376, author = {M. Dal Poz and J. Aedo Cobo and W. Van Noije and M. Zuffo}, title = {A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {2000}, issn = {1063-6862}, pages = {35}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2000.862376}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications SN - 1063-6862 SP EP A1 - M. Dal Poz, A1 - J. Aedo Cobo, A1 - W. Van Noije, A1 - M. Zuffo, PY - 2000 KW - MPEG KW - FPGA KW - Co-Design KW - VHDL KW - iDCT KW - Set-Top-Box KW - Reconfigurable Computing KW - Microprocessor KW - HDTV KW - Instruction Set KW - RISC KW - cable TV VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

M. Dal Poz, University of Sao Paulo

J. Aedo Cobo, University of Sao Paulo

W. Van Noije, University of Sao Paulo

M. Zuffo, University of Sao Paulo

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2000.862376

We propose the definition and evaluation of an instruction set designed and tuned for multimedia applications on a Digital Set-Top-Box. The proposed instruction set had its performance evaluated in software and hardware to obtain the best cost/benefit relationship referring to performance and silicon chip area. An instruction set was obtained enhancing the performance of iDCT algorithms to achieve the needs of real time MPEG-2 video decompression and to have an extra processing power available for future more complex algorithms (e.g., MPEG-4). A RISC basic core was modeled in VHDL and the defined instruction set was added into this core. In this way, the evaluations were made through out logical simulations, and the results of the added instructions over the algorithm performance were evaluated using high-level synthesis tools.

Index Terms:

MPEG, FPGA, Co-Design, VHDL, iDCT, Set-Top-Box, Reconfigurable Computing, Microprocessor, HDTV, Instruction Set, RISC, cable TV

Citation:

M. Dal Poz, J. Aedo Cobo, W. Van Noije, M. Zuffo, "A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications," asap, pp.35, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000

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