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1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97)
An efficient architecture for the in place fast cosine transform
Zurich, SWITZERLAND
July 14-July 16
ISBN: 0-8186-7958-1
ASCII Text
x 
 
M. Sanchez, J. Lopez, O. Plata, E.L. Zapata, "An efficient architecture for the in place fast cosine transform," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 499, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997.
 
 
BibTex
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@article{ 10.1109/ASAP.1997.606855,
author = {M. Sanchez and J. Lopez and O. Plata and E.L. Zapata},
title = {An efficient architecture for the in place fast cosine transform},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {1997},
issn = {1063-6862},
pages = {499},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606855},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - An efficient architecture for the in place fast cosine transform
SN - 1063-6862
SP
EP
A1 - M. Sanchez,
A1 - J. Lopez,
A1 - O. Plata,
A1 - E.L. Zapata,
PY - 1997
KW - discrete cosine transforms; in place fast cosine transform; image encoding; image compression; inverse cosine transform; locality; pipelining; DCT; VLSI implementation
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
M. Sanchez, Dept. of Comput. Archit., Malaga Univ., Spain
J. Lopez, Dept. of Comput. Archit., Malaga Univ., Spain
O. Plata, Dept. of Comput. Archit., Malaga Univ., Spain
E.L. Zapata, Dept. of Comput. Archit., Malaga Univ., Spain
The cosine transform (DCT) is in the core of image encoding and compression applications. We present a new architecture to efficiently compute the fast direct and inverse cosine transform which is based on reordering the butterflies after their computation. The designed architecture exploits locality, allowing pipelining between stages and saving memory (in place). The result is an efficient architecture for high speed computation of the DCT that reduces significantly the area required to VLSI implementation.
Index Terms:
discrete cosine transforms; in place fast cosine transform; image encoding; image compression; inverse cosine transform; locality; pipelining; DCT; VLSI implementation
Citation:
M. Sanchez, J. Lopez, O. Plata, E.L. Zapata, "An efficient architecture for the in place fast cosine transform," asap, pp.499, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997
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