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1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97)
ADPCM codec: from system level description to versatile HDL model
Zurich, SWITZERLAND
July 14-July 16
ISBN: 0-8186-7958-1
ASCII Text
x 
 
H. Dawid, K.-J. Koch, J. Stahl, "ADPCM codec: from system level description to versatile HDL model," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 458, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997.
 
 
BibTex
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@article{ 10.1109/ASAP.1997.606851,
author = {H. Dawid and K.-J. Koch and J. Stahl},
title = {ADPCM codec: from system level description to versatile HDL model},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {1997},
issn = {1063-6862},
pages = {458},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606851},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - ADPCM codec: from system level description to versatile HDL model
SN - 1063-6862
SP
EP
A1 - H. Dawid,
A1 - K.-J. Koch,
A1 - J. Stahl,
PY - 1997
KW - differential pulse code modulation; ADPCM codec; system level description; versatile HDL model; system complexity; architectural design exploration; design verification; design reuse; fast system simulation; behavioral synthesis; power analysis; adaptive differential pulse code modulation codec module; design constraints
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
H. Dawid, Synopsys Inc., Herzogenrath, Germany
K.-J. Koch, Synopsys Inc., Herzogenrath, Germany
J. Stahl, Synopsys Inc., Herzogenrath, Germany
Due to the rapid increase in the system complexity of modern telecommunication products, two main challenges exist for a system design flow meeting the arising demands: 1) provide a platform for fast algorithmic and architectural design exploration and optimization from system to gate level, which guarantees high quality of results (QoR) and enables full and seamless design verification; 2) provide a platform for design reuse. In this paper, we show how a design flow based on fast system simulation, behavioral synthesis and power analysis is used for the commercial implementation of an ADPCM (Adaptive Differential Pulse Code Modulation) codec module in record time, simultaneously meeting all design constraints and creating a versatile system and HDL model ready for design reuse.
Index Terms:
differential pulse code modulation; ADPCM codec; system level description; versatile HDL model; system complexity; architectural design exploration; design verification; design reuse; fast system simulation; behavioral synthesis; power analysis; adaptive differential pulse code modulation codec module; design constraints
Citation:
H. Dawid, K.-J. Koch, J. Stahl, "ADPCM codec: from system level description to versatile HDL model," asap, pp.458, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997
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