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1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97)
A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays
Zurich, SWITZERLAND
July 14-July 16
ISBN: 0-8186-7958-1
A new flexible datapath generator which allows the automated design of full-custom macros covering dedicated filter structures as well as programmable DSP cores is presented. The underlying concept combines the advantages of full-custom designs concerning power dissipation, silicon area, and throughput rate with a design effort comparable to semi-custom design styles. This is achieved by deriving all basic cells required for the macro layout from a set of so-called handcrafted leaf-cells by automatically generating the cell interconnections for each cell environment. Powerful routing routines based on a modified Lee-algorithm establish the interconnections within the cell boundaries, thereby avoiding unnecessary routing overhead. Since a small set of appropriately designed leaf-cells can cover a broad range of architectures the design effort is reduced significantly as compared to the pure full-custom style. Implementing new architectures typically requires the design of only a very small number of additional macro-specific leaf-cells for optimized core arrays. At the design entry the macro's functionality is described at word level as a so-called modified signal flow graph using VHDL. Optional parameters applied at this level provide a high degree of flexibility and support the careful optimization of the macro structure with short turnaround cycles. Moreover the datapath generator can be integrated into existing semi-custom design flows, enabling the embedding of optimized full-custom macros in overall semi-custom designs.
Citation:
M. Gansen, F. Richter, O. Weiss, T.G. Noll, "A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays," asap, pp.438, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997
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