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1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97)
Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture
Zurich, SWITZERLAND
July 14-July 16
ISBN: 0-8186-7958-1
ASCII Text
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S. Dogimont, M. Gumm, F. Mombers, D. Mlynek, A. Torielli, "Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 412, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997.
 
 
BibTex
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@article{ 10.1109/ASAP.1997.606846,
author = {S. Dogimont and M. Gumm and F. Mombers and D. Mlynek and A. Torielli},
title = {Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {1997},
issn = {1063-6862},
pages = {412},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606846},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture
SN - 1063-6862
SP
EP
A1 - S. Dogimont,
A1 - M. Gumm,
A1 - F. Mombers,
A1 - D. Mlynek,
A1 - A. Torielli,
PY - 1997
KW - motion estimation; RISC CPU; embedded controller; parallel multimedia architecture; high performance control structure; parallel motion estimation architecture; MPEG2 coding; combined MIMD-SIMD approach; ASIP; subword parallelism
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
S. Dogimont, Ecole Polytech. Federale de Lausanne, Switzerland
M. Gumm, Ecole Polytech. Federale de Lausanne, Switzerland
F. Mombers, Ecole Polytech. Federale de Lausanne, Switzerland
D. Mlynek, Ecole Polytech. Federale de Lausanne, Switzerland
A. Torielli, Ecole Polytech. Federale de Lausanne, Switzerland
In this paper, the problem of defining a high performance control structure for a parallel motion estimation architecture for MPEG2 coding is addressed. Various design and architecture choices are discussed and the final architecture is described. It represents a combined MIMD-SIMD approach which is based on a small but efficient ASIP with subword parallelism.
Index Terms:
motion estimation; RISC CPU; embedded controller; parallel multimedia architecture; high performance control structure; parallel motion estimation architecture; MPEG2 coding; combined MIMD-SIMD approach; ASIP; subword parallelism
Citation:
S. Dogimont, M. Gumm, F. Mombers, D. Mlynek, A. Torielli, "Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture," asap, pp.412, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997
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