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1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97)
Fast Arithmetic and Fault Tolerance in the FERMI System
Zurich, SWITZERLAND
July 14-July 16
ISBN: 0-8186-7958-1
Luca Breveglieri, Dipartimento di Elettronica e Informazione - Politecnico di Milan0
Luigi Dadda, Dipartimento di Elettronica e Informazione - Politecnico di Milan0
Vincenzo Piuri, Dipartimento di Elettronica e Informazione - Politecnico di Milan0
The FERMI is a data acquisition system for calorimetry experiments in high energy physics at the LHC, CERN. The system contains a large number of acquisition channels, with a precision of 16 bits and a sampling rate of 40 MHZ. A large part of the information driven by the channels is processed locally, to reduce the amount of data. This requires to cluster several channels by adding them. The paper presents the design of a fast, low cost adder chip, based on the implementation of column compression techniques, for the computation of integer addition. Since the system is operating in a radiation-hard environment, fault tolerance (namely fault detection) is implemented by means of arithmetic code.
Citation:
Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, "Fast Arithmetic and Fault Tolerance in the FERMI System," asap, pp.374, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997
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