New arithmetic coder/decoder architectures based on pipelining

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	Similar Articles Articles by R.R. Osorio Articles by J.D. Bruguera

1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97)

Zurich, SWITZERLAND

July 14-July 16

ISBN: 0-8186-7958-1

	ASCII Text	x
	R.R. Osorio, J.D. Bruguera, "New arithmetic coder/decoder architectures based on pipelining," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 106, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997.

	BibTex	x
	@article{ 10.1109/ASAP.1997.606817, author = {R.R. Osorio and J.D. Bruguera}, title = {New arithmetic coder/decoder architectures based on pipelining}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {1997}, issn = {1063-6862}, pages = {106}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606817}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - New arithmetic coder/decoder architectures based on pipelining SN - 1063-6862 SP EP A1 - R.R. Osorio, A1 - J.D. Bruguera, PY - 1997 KW - VLSI; arithmetic coder/decoder architectures; pipelining; VLSI architectures; arithmetic encoding; arithmetic decoding; multilevel images; cycle length VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

R.R. Osorio, Dept. of Electron. & Comput., Santiago de Compostela Univ., Spain

J.D. Bruguera, Dept. of Electron. & Comput., Santiago de Compostela Univ., Spain

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606817

In this paper we present new VLSI architectures for the arithmetic encoding and decoding of multilevel images. In these algorithms the speed is limited by their recursive natures and the arithmetic and memory access operations. They become specially critical in the case of decoding. In order to reduce the cycle length we propose working with two executions of the algorithm which alternate in the use of the pipelined hardware with a minimum increase in its cost.

Index Terms:

VLSI; arithmetic coder/decoder architectures; pipelining; VLSI architectures; arithmetic encoding; arithmetic decoding; multilevel images; cycle length

Citation:

R.R. Osorio, J.D. Bruguera, "New arithmetic coder/decoder architectures based on pipelining," asap, pp.106, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997

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