A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor

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	Similar Articles Articles by Carolina Miro Articles by Nicolas Darbel Articles by Renaud Pacalet Articles by Valerie Paquet

1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97)

Zurich, SWITZERLAND

July 14-July 16

ISBN: 0-8186-7958-1

	ASCII Text	x
	Carolina Miro, Nicolas Darbel, Renaud Pacalet, Valerie Paquet, "A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 86, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997.

	BibTex	x
	@article{ 10.1109/ASAP.1997.606815, author = {Carolina Miro and Nicolas Darbel and Renaud Pacalet and Valerie Paquet}, title = {A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {1997}, issn = {1063-6862}, pages = {86}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606815}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor SN - 1063-6862 SP EP A1 - Carolina Miro, A1 - Nicolas Darbel, A1 - Renaud Pacalet, A1 - Valerie Paquet, PY - 1997 VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606815

This paper presents a circuit dedicated to real time geometrical transforms of pictures. The supported transforms are third degree polynomials of two variables. The post-processing is performed by a bilinear filter. An embedded DSP core is in charge of high level, low rate, control tasks while a set of hard wired units is in charge of computing intensive low level tasks.

Citation:

Carolina Miro, Nicolas Darbel, Renaud Pacalet, Valerie Paquet, "A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor," asap, pp.86, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997

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