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1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97)
A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor
Zurich, SWITZERLAND
July 14-July 16
ISBN: 0-8186-7958-1
This paper presents a circuit dedicated to real time geometrical transforms of pictures. The supported transforms are third degree polynomials of two variables. The post-processing is performed by a bilinear filter. An embedded DSP core is in charge of high level, low rate, control tasks while a set of hard wired units is in charge of computing intensive low level tasks.
Citation:
Carolina Miro, Nicolas Darbel, Renaud Pacalet, Valerie Paquet, "A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor," asap, pp.86, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997
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