Buffer size optimization for full-search block matching algorithms

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	Similar Articles Articles by Yuan-Hau Yeh Articles by Chen-Yi Lee

1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97)

Zurich, SWITZERLAND

July 14-July 16

ISBN: 0-8186-7958-1

	ASCII Text	x
	Yuan-Hau Yeh, Chen-Yi Lee, "Buffer size optimization for full-search block matching algorithms," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 76, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997.

	BibTex	x
	@article{ 10.1109/ASAP.1997.606814, author = {Yuan-Hau Yeh and Chen-Yi Lee}, title = {Buffer size optimization for full-search block matching algorithms}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {1997}, issn = {1063-6862}, pages = {76}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606814}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - Buffer size optimization for full-search block matching algorithms SN - 1063-6862 SP EP A1 - Yuan-Hau Yeh, A1 - Chen-Yi Lee, PY - 1997 KW - image processing; buffer size optimization; full-search block matching algorithms; VLSI architectures; optimized buffer size; dependency graph analysis; internal buffer size; I/O bandwidth constraint; systematic design procedure VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

Yuan-Hau Yeh, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Chen-Yi Lee, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606814

This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buffer size under minimal I/O bandwidth constraint. As a result, a systematic design procedure for buffer optimization is derived to reduce realization cost.

Index Terms:

image processing; buffer size optimization; full-search block matching algorithms; VLSI architectures; optimized buffer size; dependency graph analysis; internal buffer size; I/O bandwidth constraint; systematic design procedure

Citation:

Yuan-Hau Yeh, Chen-Yi Lee, "Buffer size optimization for full-search block matching algorithms," asap, pp.76, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997

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