Realization of a nonlinear digital filter on a DSP array processor

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	Similar Articles Articles by H. Kwan Articles by E.J. Powers Articles by E.E. Swartzlander, Jr.

1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97)

Zurich, SWITZERLAND

July 14-July 16

ISBN: 0-8186-7958-1

	ASCII Text	x
	H. Kwan, E.J. Powers, E.E. Swartzlander, Jr., "Realization of a nonlinear digital filter on a DSP array processor," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 24, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997.

	BibTex	x
	@article{ 10.1109/ASAP.1997.606809, author = {H. Kwan and E.J. Powers and E.E. Swartzlander, Jr.}, title = {Realization of a nonlinear digital filter on a DSP array processor}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {1997}, issn = {1063-6862}, pages = {24}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606809}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - Realization of a nonlinear digital filter on a DSP array processor SN - 1063-6862 SP EP A1 - H. Kwan, A1 - E.J. Powers, A1 - E.E. Swartzlander, Jr., PY - 1997 KW - digital signal processing chips; nonlinear digital filter; performance evaluation; third-order Volterra digital filtering algorithm; AT&T DSP-3 parallel processor; time-skewing; nonlinear communication channel equalization; 64-QAM signal constellation VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

H. Kwan, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

E.J. Powers, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

E.E. Swartzlander, Jr., Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606809

This paper presents the performance evaluation of a fast third-order Volterra digital filtering algorithm mapped onto an AT&T DSP-3 parallel processor. Five different implementations are considered. Speed-up results indicate that the "time-skewing" method is currently the fastest. An application to nonlinear communication channel equalization using a 64-QAM signal constellation is presented.

Index Terms:

digital signal processing chips; nonlinear digital filter; performance evaluation; third-order Volterra digital filtering algorithm; AT&T DSP-3 parallel processor; time-skewing; nonlinear communication channel equalization; 64-QAM signal constellation

Citation:

H. Kwan, E.J. Powers, E.E. Swartzlander, Jr., "Realization of a nonlinear digital filter on a DSP array processor," asap, pp.24, 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'97), 1997

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