1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96)
Latency-constrained Resynchronization for Multiprocessor DSP Implementation
Chicago, IL
August 19-August 23
ISBN: 0-8186-7542-X
S. S. Bhattacharyya, Semiconductor Research Laboratory, Hitachi America, Ltd. shuvra@halsrl.com
S. Sriram, DSP R&D Center, Texas Instruments Incorporated sriram@hc.ti.com
E. A. Lee, University of California at Berkeley eal@eecs.berkeley.edu, fax: (510)642-2739.
Resynchronization is a post-optimization for static multiprocessor schedules in which extraneous synchronization operations are introduced in such a way that the number of original synchronizations that consequently become redundant significant exceeds the number of additional synchronizations. Redundant synchronizations are synchronization operations whose corresponding sequencing requirements are enforced completely by other synchronizations in the system. The amount of run-time overhead required for synchronization can be reduced significantly by eliminating redundant synchronizations. However, since additional serialization is imposed by the new synchronizations, resynchronization can produce significant increase in latency. This paper addresses the problem of computing an optimal resynchronization (one that results in the lowest average rate at which synchronization operations have to be performed) among all resynchronizations that do not increase the latency beyond a prespecified upper bound. Our study is based in the context of self-timed execution of iterative dataflow programs, which is an implementation model that has been applied extensively for digital signal processing systems.
Index Terms:
static multi-processor schedules, synchronization overhead, latency, iterative dataflow programs, self-timed execution
Citation:
S. S. Bhattacharyya, S. Sriram, E. A. Lee, "Latency-constrained Resynchronization for Multiprocessor DSP Implementation," asap, pp.365, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996