Rapid Prototyping of Reconfigurable Coprocessors

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Naren Narasimhan Articles by Vinoo Srinivasan Articles by Madhavi Vootukuru Articles by Jeff Walrath Articles by Sriram Govindarajan Articles by Ranga Vemuri

1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96)

Chicago, IL

August 19-August 23

ISBN: 0-8186-7542-X

	ASCII Text	x
	Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeff Walrath, Sriram Govindarajan, Ranga Vemuri, "Rapid Prototyping of Reconfigurable Coprocessors," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 303, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996.

	BibTex	x
	@article{ 10.1109/ASAP.1996.542825, author = {Naren Narasimhan and Vinoo Srinivasan and Madhavi Vootukuru and Jeff Walrath and Sriram Govindarajan and Ranga Vemuri}, title = {Rapid Prototyping of Reconfigurable Coprocessors}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {1996}, issn = {1063-6862}, pages = {303}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542825}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - Rapid Prototyping of Reconfigurable Coprocessors SN - 1063-6862 SP EP A1 - Naren Narasimhan, A1 - Vinoo Srinivasan, A1 - Madhavi Vootukuru, A1 - Jeff Walrath, A1 - Sriram Govindarajan, A1 - Ranga Vemuri, PY - 1996 KW - Hardware-Software Co-design KW - Coprocessors KW - Software Profiling KW - Prototyping KW - JPEG KW - High-level Synthesis VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

Naren Narasimhan, University of Cincinnati

Vinoo Srinivasan, University of Cincinnati

Madhavi Vootukuru, University of Cincinnati

Jeff Walrath, University of Cincinnati

Sriram Govindarajan, University of Cincinnati

Ranga Vemuri, University of Cincinnati

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542825

In this paper we present a hardware-software codesign methodology. We describe the process of codesign using a JPEG-like still image compression system as a case study. The hardware components are targeted to execute on a reconfigurable hardware coprocessor. The coprocessor is composed of one or more FPGAs, a RAM and logic to interface with a general purpose computer. The software tasks execute on the general purpose computer. Central to our codesign process are the use of software profiling and high-level estimation and synthesis tools. We describe the process of tradeoff analysis and hardware task selection in detail. Finally, this paper presents detailed experimental results on design performance gathered throughout the codesign cycle.

Index Terms:

Hardware-Software Co-design, Coprocessors, Software Profiling, Prototyping, JPEG, High-level Synthesis

Citation:

Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeff Walrath, Sriram Govindarajan, Ranga Vemuri, "Rapid Prototyping of Reconfigurable Coprocessors," asap, pp.303, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.