1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96) Hardware Synthesis From Encapsulated Verilog Modules Chicago, IL August 19-August 23 ISBN: 0-8186-7542-X
This paper discusses experience with synthesis from a Verilog writing style using encapsulated modules. The method is shown to be capable of significant advantages in reduction of code complexity, re-use of submodules, and automatic inference of control. In order to pass synthesis and low level simulation, care must be taken in the translation of the encapsulated modules through an intermediate style accessible to industry synthesizers. If the encapsulated modules are edge activated then the control points need to be staggered in time through the clock cycle as control is passed down through the hierarchy. Examples are given of a such an intermediate style which is acceptable to synthesis and low level simulation. A conclusion discusses other implications of adapting the objective style to hardware design.
Index Terms:
logic design; hardware description languages; computational complexity; inference mechanisms; hardware synthesis; encapsulated Verilog modules; Verilog writing style; code complexity; automatic inference of control; low level simulation; control points; clock cycle
Citation:
D.R. Smith, "Hardware Synthesis From Encapsulated Verilog Modules," asap, pp.284, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb