This paper discusses experience with synthesis from a Verilog writing style using encapsulated modules. The method is shown to be capable of significant advantages in reduction of code complexity, re-use of submodules, and automatic inference of control. In order to pass synthesis and low level simulation, care must be taken in the translation of the encapsulated modules through an intermediate style accessible to industry synthesizers. If the encapsulated modules are edge activated then the control points need to be staggered in time through the clock cycle as control is passed down through the hierarchy. Examples are given of a such an intermediate style which is acceptable to synthesis and low level simulation. A conclusion discusses other implications of adapting the objective style to hardware design.