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1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96)
A Common Architecture For The DWT and IDWT
Chicago, IL
August 19-August 23
ISBN: 0-8186-7542-X
M. Vishwanath, Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA
R.M. Owens, Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA
This paper presents an architecture which is equally efficient at computing both the discrete wavelet transform (the DWT) and the inverse discrete wavelet transform (the IDWT). Given the seemingly fundamental difference between the structure of a DWT filter bank and the structure of an IDWT filter bank, it is somewhat surprising that such an architecture can be derived. Our architecture allows the building of a single chip which can efficiently compute both transforms. Tandem use of the architecture(?> DWT?> IDWT?>) is simplified by the fact that the j'th octave is generated by the architecture when it is in DWT mode at the sane rate at which it is consumed by the architecture when it is in IDWT mode.
Index Terms:
wavelet transforms; digital signal processing chips; discrete wavelet transform; inverse discrete wavelet transform; filter bank; single chip; j'th octave
Citation:
M. Vishwanath, R.M. Owens, "A Common Architecture For The DWT and IDWT," asap, pp.193, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996
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