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1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96)
High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining
Chicago, IL
August 19-August 23
ISBN: 0-8186-7542-X
ASCII Text
x 
 
M. Boo, F. Arguello, J.D. Bruguera, E.L. Zapata, "High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 165, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996.
 
 
BibTex
x
 
@article{ 10.1109/ASAP.1996.542811,
author = {M. Boo and F. Arguello and J.D. Bruguera and E.L. Zapata},
title = {High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {1996},
issn = {1063-6862},
pages = {165},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542811},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining
SN - 1063-6862
SP
EP
A1 - M. Boo,
A1 - F. Arguello,
A1 - J.D. Bruguera,
A1 - E.L. Zapata,
PY - 1996
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
M. Boo, Univ. Santiago de Compostela elmboo@usc.es
F. Arguello, Univ. Santiago de Compostela elmboo@usc.es
J.D. Bruguera, Univ. Santiago de Compostela elmboo@usc.es
E.L. Zapata, Univ. Santiago de Compostela elmboo@usc.es
The main part of the Viterbi Algorithm is a nonlinear feedback loop which presents a bottleneck for high-speed implementations. We present a novel scheduling scheme that allows increasing the available speed of the system. This is done through the utilization of look-ahead techniques to compute non--sequential data and, in this way, break the recursivity of the algorithm. This permits introducing pipelining. As a result, we obtain a speed growth comparable to previous parallel solutions, but with less hardware cost.
Citation:
M. Boo, F. Arguello, J.D. Bruguera, E.L. Zapata, "High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining," asap, pp.165, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996
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