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1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96)
A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation
Chicago, IL
August 19-August 23
ISBN: 0-8186-7542-X
ASCII Text
x 
 
H. Yeo, Y.H. Hu, "A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 122, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996.
 
 
BibTex
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@article{ 10.1109/ASAP.1996.542807,
author = {H. Yeo and Y.H. Hu},
title = {A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {1996},
issn = {1063-6862},
pages = {122},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542807},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation
SN - 1063-6862
SP
EP
A1 - H. Yeo,
A1 - Y.H. Hu,
PY - 1996
KW - motion estimation; power consumption; video signal processing; matching criterion; low power architecture; real-time block based motion estimation; power consumption; video signals; binary level matching criterion; bit-wise comparison; processor level design; combinational logic; total power consumption
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
H. Yeo, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Y.H. Hu, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
In recent years, minimizing the power consumption has become a key issue in the design of portable electronic devices. In this paper, low power architecture which can support the real time motion estimation of video signals is presented. The architecture is based on a binary level matching criterion which performs a bit-wise comparison. The processor level design based on simple combinational logic using the binary level matching criterion has been introduced. Compared with the existing architectures, the proposed architecture delivers higher throughput rate, requires fewer input/output lines, and reduces the total power consumption.
Index Terms:
motion estimation; power consumption; video signal processing; matching criterion; low power architecture; real-time block based motion estimation; power consumption; video signals; binary level matching criterion; bit-wise comparison; processor level design; combinational logic; total power consumption
Citation:
H. Yeo, Y.H. Hu, "A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation," asap, pp.122, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996
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