A flexible block matching motion estimation architecture is described. The block size can be adaptively refined with blocks of 8 x 8, 16 x 16 and 32 x 32 pixels or can be set to one of these sizes without significant loss in efficiency in comparison with standard block matching. The chip performs block matching on a search area of +- 15 vertically and horizontally for a block size of up to 32 x 32. For larger search areas devices can be cascaded. Full search can be processed as well as fast algorithms with an additional external RAM and a RISC processor. Sub-pel precision motion vectors can be derived using a smaller search area or cascading devices. The chip will have a computational power of more than 200 GOPS and a die size of 170 mm2 in a 0.5-um CMOS technology.