Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline

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	Similar Articles Articles by K.P. Acken Articles by M.J. Irwin Articles by R.M. Owens Articles by A.K. Garga

1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96)

Chicago, IL

August 19-August 23

ISBN: 0-8186-7542-X

	ASCII Text	x
	K.P. Acken, M.J. Irwin, R.M. Owens, A.K. Garga, "Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 65, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996.

	BibTex	x
	@article{ 10.1109/ASAP.1996.542802, author = {K.P. Acken and M.J. Irwin and R.M. Owens and A.K. Garga}, title = {Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {1996}, issn = {1063-6862}, pages = {65}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542802}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline SN - 1063-6862 SP EP A1 - K.P. Acken, A1 - M.J. Irwin, A1 - R.M. Owens, A1 - A.K. Garga, PY - 1996 KW - data visualisation; virtual reality; computer graphics; matrix multiplication; floating point arithmetic; architectural optimizations; floating point multiply-accumulate unit; graphics pipeline; scientific visualization; virtual reality; three-dimensional graphics engines; normalized space; parallelism; matrix multiplications VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

K.P. Acken, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

A.K. Garga, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542802

Scientific visualization and virtual reality have pushed three-dimensional graphics engines to their limits for updating scenes in real-time. One bottleneck of graphic systems is the transformation of an object's vertices into normalized space based on an evaluated transformation stack. This operation as often done in floating point, requiring a fast floating point multiply-accumulate unit. This paper presents architectural optimizations to a graphics pipeline floating point multiply-accumulate unit by using block floating point and parallelism to bypass or merge trivial operations in the matrix multiplications.

Index Terms:

data visualisation; virtual reality; computer graphics; matrix multiplication; floating point arithmetic; architectural optimizations; floating point multiply-accumulate unit; graphics pipeline; scientific visualization; virtual reality; three-dimensional graphics engines; normalized space; parallelism; matrix multiplications

Citation:

K.P. Acken, M.J. Irwin, R.M. Owens, A.K. Garga, "Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline," asap, pp.65, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996

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