1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96) Kestrel: A Programmable Array for Sequence Analysis Chicago, IL August 19-August 23 ISBN: 0-8186-7542-X
Kestrel is a programmable linear systolic array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, and efficient communication using Systolic Shared Registers. This paper describes Kestrel's functional units in detail, and examines each of their effects on system performance. With prototypes currently in the works, we expect to complete a full Kestrel array, with between 512 and 1024 processing elements, in 1997.
Citation:
Jeffrey D. Hirschberg, Richard Hughey, Kevin Karplus, Don Speck, "Kestrel: A Programmable Array for Sequence Analysis," asap, pp.25, 1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96), 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||